entity extensorSemSinal is
	port (
		entrada : in bit_vector (15 downto 0);
		saida : out bit_vector (31 downto 0)
	);
end extensorSemSinal;

architecture arc_extensorSemSinal of extensorSemSinal is
	
begin

			saida(15 downto 0) <= entrada(15 downto 0);
			saida(31 downto 16) <= "0000000000000000";

end arc_extensorSemSinal;